1. Field of the Disclosure
The present disclosure is generally directed to instruction processing and, more particularly, to multithreading in a processing pipeline.
2. Description of the Related Art
Multithreaded processing devices often implement coarse multithreading whereby a processing pipeline is dedicated to a single thread at any given time. In the event of a thread switch, the processing pipeline is flushed of the current thread and instructions for the newly-selected thread are processed by the processing pipeline. The process of flushing the processing pipeline can consume numerous cycles and therefore decrease overall instruction execution bandwidth. As an alternative, some multithreaded processing devices implement finer multithreading whereby instructions from multiple threads can be multiplexed at the beginning of the processing pipeline. However, the order in which the threads are selected for processing at the beginning of the processing pipeline typically is maintained for all subsequent stages of the pipeline. This can lead to processing inefficiencies in the event that a particular stage of the processing pipeline is idled by an instruction operation while waiting for some external event (e.g., the return of data from memory). Accordingly, a more flexible thread selection technique in a processing pipeline would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.